Athlon model 8 and 10 set full L2 cache



The L2 bridge controls the amount of cache that the CPU has. Some CPUs, such as the Applebred Duron and the Thorton Athlon XP have more cache on the die than what is enabled. In some cases, this extra cache was disabled as it was tested and was defective, but in other cases this extra cache is not defective and can be re-enabled safely (though may require a higher than normal vcore).

Since there are multiple configurations for the same cache size, it is thought that different configurations use different parts of the cache. So if one bridge configuration does not result in a stable CPU, then using a different one with the same total L2 size may result in a stable CPU.

The bridges can be rejoined or the cuts can be filled with a conductive material. Rejoining is recommended as removing the conductive material can be difficult if the cache turns out not to be fully functional.

The available L2 bridge configurations are:
L2 cache sizeL2 configuration
512kb (model 10)
256kb (model 8)
256kb
256kb
256kb
128kb
128kb
128kb
128kb
L2 cache sizeL2 configuration
64kb
 
64kb
64kb
64kb
64kb
64kb
64kb
64kb


See also:
Week 39 and newer die-locked CPUs